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1 july 2013 cmos syncfifo? 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 idt72420 idt72200 idt72210 idt72220 idt72230 idt72240 idt, idt logo are registered trademarks of integrated device technology, inc. the syncfifo is a trademark of integrated device technology, inc. commercial temperature range ? 2013 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-2680/6 description: the idt72420/72200/72210/72220/72230/72240 syncfifo? are very high-speed, low-power first-in, first-out (fifo) memories with clocked read and write controls. these devices have a 64, 256, 512, 1,024, 2,048, and 4,096 x 8-bit memory array, respectively. these fifos are applicable for a wide variety of data buffering needs, such as graphics, local area networks (lans), and interprocessor communication. these fifos have 8-bit input and output ports. the input port is controlled by a free-running clock (wclk), and a write enable pin ( wen ). data is written into the synchronous fifo on every clock when wen is asserted. the output port is controlled by another clock pin (rclk) and a read enable pin ( ren ). the read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. an output enable pin ( oe ) is provided on the read port for three-state control of the output. these synchronous fifos have two endpoint flags, empty ( ef ) and full ( ff ). two partial flags, almost-empty ( ae ) and almost-full ( af ), are provided for improved system control. the partial ( ae ) flags are set to empty+7 and full- 7 for ae and af respectively. these fifos are fabricated using high-speed submicron cmos technol- ogy. functional block diagram features: ? ? ? ? ? 64 x 8-bit organization (idt72420) ? ? ? ? ? 256 x 8-bit organization (idt72200) ? ? ? ? ? 512 x 8-bit organization (idt72210) ? ? ? ? ? 1,024 x 8-bit organization (idt72220) ? ? ? ? ? 2,048 x 8-bit organization (idt72230) ? ? ? ? ? 4,096 x 8-bit organization (idt72240) ? ? ? ? ? 10 ns read/write cycle time (idt72420/72200/72210/72220/72230/ 72240) ? ? ? ? ? read and write clocks can be asynchronous or coincidental ? ? ? ? ? dual-ported zero fall-through time architecture ? ? ? ? ? empty and full flags signal fifo status ? ? ? ? ? almost-empty and almost-full flags set to empty+7 and full-7, respectively ? ? ? ? ? output enable puts output data bus in high-impedance state ? ? ? ? ? produced with advanced submicron cmos technology ? ? ? ? ? available in 28-pin 300 mil plastic dip ? ? ? ? ? for surface mount product please see the idt72421/72201/72211/ 72221/72231/72241 data sheet ? ? ? ? ? green parts available, see ordering information input register output register ram array 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 flag logic read pointer read control logic write control logic write pointer reset logic wclk rclk ren d0 - d7 q0 - q7 rs oe ff af ae ef wen 2680 drw01
2 commercial temperature range idt72420/72200/72210/72220/72230/72240 cmos syncfifo? 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 pin configuration symbol name i/o description d 0 - d 7 data inputs i data inputs for a 8-bit bus. rs reset i when rs is set low, internal read and write pointers are set to the first location of the ram array, ff and af go high, and ae and ef go low. a reset is required before an initial write after power-up. wclk write clock i data is written into the fifo on a low-to-high transition of wclk when wen is asserted. wen write enable i when wen is low, data is written into the fifo on every low-to-high transition of wclk. data will not be written into the fifo if the ff is low. q 0 - q 7 data outputs o data outputs for a 8-bit bus. rclk read clock i data is read from the fifo on a low-to-high transition of rclk when ren is asserted. ren read enable i when ren is low, data is read from the fifo on every low-to-high transition of rclk. data will not be read from the fifo if the ef is low. oe output enable i when oe is low, the data output bus is active. if oe is high, the output data bus will be in a high-impedance state. ef empty flag o when ef is low, the fifo is empty and further data reads from the output are inhibited. when ef is high, the fifo is not empty. ef is synchronized to rclk. ae almost-empty flag o when ae is low, the fifo is almost empty based on the offset empty+7. ae is synchronized to rclk. af almost-full flag o when af is low, the fifo is almost full based on the offset full-7. af is synchronized to wclk. ff full flag o when ff is low, the fifo is full and further data writes into the input are inhibited. when ff is high, the fifo is not full. ff is synchronized to wclk. v cc power one +5 volt power supply pin. gnd ground one 0 volt ground pin. pin descriptions plastic thin dip (p28-2, order code: tp) top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d4 d3 d2 d1 d0 af ae gnd rclk ren oe ef ff q0 d5 d6 d7 rs wen wclk vcc q7 q6 q5 q4 q3 q2 q1 2680 drw02
3 commercial temperature range idt72420/72200/72210/72220/72230/72240 cmos syncfifo? 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 absolute maximum ratings (1) recommended operating conditions note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics (commercial: v cc = 5v 10%, t a = 0 c to +70 c) notes: 1. measurements with 0.4 v in v cc . 2. oe v ih, 0.4 v out v cc . 3. tested with outputs open (i out = 0). 4. rclk and wclk toggle at 20 mhz and data inputs switch at 10 mhz. 5. typical i cc1 = 1.7 + 0.7*f s + 0.02*c l *f s (in ma). these equations are valid under the following conditions: v cc = 5v, t a = 25 c, f s = wclk frequency = rclk frequency (in mhz, using ttl levels), data switching at f s /2, c l = capacitive load (in pf). 6. all inputs = v cc - 0.2v or gnd + 0.2v, except rclk and wclk, which toggle at 20 mhz. idt72420 idt72200 idt72210 idt72220 idt72230 idt72240 commercial t clk = 10, 15, 25 ns symbol parameter min. typ. max. unit i li (1) input leakage current (any input) ?1 ? 1 a i lo (2) output leakage current ?10 ? 10 a v oh output logic ?1? voltage, i oh = ?2 ma 2.4 ? ? v v ol output logic ?0? voltage, i ol = 8 ma ? ? 0.4 v i cc1 (3,4,5) active power supply current ? ? 40 ma i cc2 (3,6) standby current ? ? 5 ma symbol rating com'l & ind'l unit v term terminal voltage with ?0.5 to +7.0 v respect to gnd t stg storage temperature ?55 to +125 c i out dc output current ?50 to +50 ma symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v commercial gnd supply voltage 0 0 0 v v ih input high voltage 2.0 ? ? v commercial v il input low voltage ? ? 0.8 v commercial t a operating temperature 0 ? 70 c commercial
4 commercial temperature range idt72420/72200/72210/72220/72230/72240 cmos syncfifo? 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 ac electrical characteristics (commercial: v cc = 5v 10%, t a = 0 c to + 70 c) commercial idt72420l10 idt72420l15 idt72420l25 idt72200l10 idt72200l15 idt72200l25 idt72210l10 idt72210l15 idt72210l25 idt72220l10 idt72220l15 idt72220l25 idt72230l10 idt72230l15 idt72230l25 idt72240l10 idt72240l15 idt72240l25 symbol parameter min. max. min. max. min. max. unit f s clock cycle frequency ? 100 ? 66.7 ? 40 m h z t a data access time 2 6.5 2 10 2 15 ns t clk clock cycle time 10 ? 15 ? 25 ? ns t clkh clock high time 4.5 ? 6 ? 10 ? ns t clkl clock low time 4.5 ? 6 ? 10 ? ns t ds data setup time 3 ? 4 ? 6 ? ns t dh data hold time 0.5 ? 1 ? 1 ? ns t ens enable setup time 3 ? 4 ? 6 ? ns t enh enable hold time 0.5 ? 1 ? 1 ? ns t rs reset pulse width (1) 10 ? 15 ? 15 ? ns t rss reset setup time 8 ? 10 ? 15 ? ns t rsr reset recovery time 8 ? 10 ? 15 ? ns t rsf reset to flag and output time ? 10 ? 15 ? 25 ns t olz output enable to output in low-z (2) 0 ?0?0?ns t oe output enable to output valid 2 6 3 8 3 13 ns t ohz output enable to output in high-z (2) 2 638313ns t wff write clock to full flag ? 6.5 ? 10 ? 15 ns t ref read clock to empty flag ? 6.5 ? 10 ? 15 ns t af write clock to almost-full flag ? 6.5 ? 10 ? 15 ns t ae read clock to almost-empty flag ? 6.5 ? 10 ? 15 ns t skew1 skew time between read clock & write clock for 4 ? 6 ? 10 ? ns empty flag & full flag t skew2 skew time between read clock & write clock for 10 ? 15 ? 18 ? ns almost-empty flag & almost-full flag notes: 1. pulse widths less than minimum values are not allowed. 2. values guaranteed by design, not currently tested. or equivalent circuit figure 1. output load *includes jig and scope capacitances. input pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 1 symbol parameter conditions max. unit c in input capacitance v in = 0v 10 pf c out output capacitance v out = 0v 10 pf (1, 2) (2) notes: 1. with output deselected. ( oe vih) 2. characterized values, not currently tested. ac test conditions capacitance (t a = +25 c, f = 1.0 mhz) 30pf* 1.1k 5v 680 d.u.t. 2680 drw03
5 commercial temperature range idt72420/72200/72210/72220/72230/72240 cmos syncfifo? 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 when all the data has been read from the fifo, the empty flag ( ef ) will go low, inhibiting further read operations. once a valid write operation has been accomplished, the empty flag ( ef ) will go high after t ref and a valid read can begin. read enable ( ren ) is ignored when the fifo is empty. output enable ( oe ) ? when output enable ( oe ) is enabled (low), the parallel output buffers receive data from the output register. when output enable ( oe ) is disabled (high), the q output data bus is in a high- impedance state. outputs: full flag ( ff ) ? the full flag ( ff ) will go low, inhibiting further write operation, when the device is full. if no reads are performed after reset ( rs ), the full flag ( ff ) will go low after 64 writes for the idt72420, 256 writes for the idt72200, 512 writes for the idt72210, 1,024 writes for the idt72220, 2,048 writes for the idt72230, and 4,096 writes for the idt72240. the full flag ( ff ) is synchronized with respect to the low-to-high transition of the write clock (wclk). empty flag ( ef ) ? the empty flag ( ef ) will go low, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. the empty flag ( ef ) is synchronized with respect to the low-to-high transition of the read clock (rclk). almost-full flag ( af ) ? the almost-full flag ( af ) will go low when the fifo reaches the almost-full condition. if no reads are performed after reset ( rs ), the almost-full flag ( af ) will go low after 57 writes for the idt72420, 249 writes for the idt72200, 505 writes for the idt72210, 1,017 writes for the idt72220, 2,041 writes for the idt72230 and 4,089 writes for the idt72240. the almost-full flag ( af ) is synchronized with respect to the low-to- high transition of the write clock (wclk). almost-empty flag ( ae ) ? the almost-empty flag ( ae ) will go low when the fifo reaches the almost-empty condition. if no reads are performed after reset ( rs ), the almost-empty flag ( ae ) will go high after 8 writes for the idt72420, idt72200, idt72210, idt72220, idt72230 and idt72240. the almost-empty flag ( ae ) is synchronized with respect to the low- to-high transition of the read clock (rclk). data outputs (q 0 ?q 7 ) ? data outputs for 8-bit wide data. signal descriptions inputs: data in (d 0 ?d 7 ) ? data inputs for 8-bit wide data. controls: reset ( rs ) ? reset is accomplished whenever the reset ( rs ) input is taken to a low state. during reset, both internal read and write pointers are set to the first location. a reset is required after power up before a write operation can take place. the full flag ( ff ) and almost-full flag ( af ) will be reset to high after t rsf . the empty flag ( ef ) and almost-empty flag ( ae ) will be reset to low after t rsf . during reset, the output register is initialized to all zeros. write clock (wclk) ? a write cycle is initiated on the low-to-high transition of the write clock (wclk). data setup and hold times must be met in respect to the low-to-high transition of the write clock. the full flag ( ff ) and almost-full flag ( af ) are synchronized with respect to the low- to-high transition of the write clock. the write and read clocks can be asynchronous or coincident. write enable ( wen ) ? when write enable ( wen ) is low, data can be loaded into the input register and ram array on the low-to-high transition of every write clock (wclk). data is stored in the ram array sequentially and independently of any on-going read operation. when write enable ( wen ) is high, the input register holds the previous data and no new data is allowed to be loaded into the register. to prevent data overflow, the full flag ( ff ) will go low, inhibiting further write operations. upon the completion of a valid read cycle, the full flag ( ff ) will go high after t wff , allowing a valid write to begin. write enable ( wen ) is ignored when the fifo is full. read clock (rclk) ? data can be read on the outputs on the low-to- high transition of the read clock (rclk). the empty flag ( ef ) and almost-empty flag ( ae ) are synchronized with respect to the low-to-high transition of the read clock. the write and read clocks can be asynchronous or coincident. read enable ( ren ) ? when read enable ( ren ) is low, data is read from the ram array to the output register on the low-to-high transition of the read clock (rclk). when read enable ( ren ) is high, the output register holds the previous data and no new data is allowed to be loaded into the register. number of words in fifo idt72420 idt72200 idt72210 idt72220 idt72230 idt72240 ff af ae ef 0000 0 0hhll 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 h h l h 8 to 56 8 to 248 8 to 504 8 to 1,016 8 to 2,040 8 to 4,088 hhhh 57 to 63 249 to 255 505 to 511 1,017 to 1,023 2,041 to 2,047 4,089 to 4,095 h l h h 64 256 512 1,024 2,048 4,096 l l h h table 1 ? status flags
6 commercial temperature range idt72420/72200/72210/72220/72230/72240 cmos syncfifo? 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 note: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge for ff to change during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk edge. figure 3. write cycle timing notes: 1. after reset, the outputs will be low if oe = 0 and three-state if oe = 1. 2. the clocks (rclk, wclk) can be free-running during reset. figure 2. reset timing t rs t rsr rs ren t rsf t rsf ef , ae ff , af q 0 - q 7 wen t rss t rsf t rsr t rss oe = 1 (1) oe = 0 2680 drw 04 wclk d 0 - d 7 wen ff t clk t clkh t clkl t ds t ens t dh t enh t wff t wff data in valid rclk (1) t skew1 ren no operation 2680 drw 05
7 commercial temperature range idt72420/72200/72210/72220/72230/72240 cmos syncfifo? 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 wclk d 0 - d 7 wen rclk ef q 0 - q 7 ren t ds t skew1 t frl t ens t ref t a d0 d1 (first valid write) t olz (1) t ens d2 d3 oe t oe t a d0 d1 2680 drw 07 note: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge for ef to change during the current clock cycle. if the time between the rising edge of wclk and the rising edge of rclk is less than t skew1 , then ef may not change state until the next rclk edge. figure 4. read cycle timing figure 5. first data word latency timing note: 1. when t skew1 minimum specification, t frl maximum = t clk + t skew1 when t skew1 < minimum specification, t frl maximum = 2t clk + t skew1 or t clk + t skew1 the latency timing apply only at the empty boundary ( ef = low). no operation rclk ren ef t clk t clkh t clkl t ens t enh t ref t ref valid data t a t olz t oe q 0 - q 7 oe wclk (1) t skew1 wen t ohz 2680 drw 06
8 commercial temperature range idt72420/72200/72210/72220/72230/72240 cmos syncfifo? 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 figure 6. full flag timing note: 1. when t skew1 minimum specification, t frl maximum = t clk + t skew1 when t skew1 < minimum specification, t frl maximum = 2t clk + t skew1 or t clk + t skew1 the latency timing apply only at the empty boundary ( ef = low). figure 7. empty flag timing wclk d 0 - d 7 wen rclk ff t skew1 t wff data write ren t enh t ds t skew1 t ens no write no write t a low oe t ens t wff t ens q 0 - q 7 t enh t a t ens t wff next data read data read data in output register 2680 drw 08 no write wclk d 0 - d 7 wen rclk ef q 0 - q 7 oe t ds t ens t ref t a data write 1 t enh t ref t ds t ens data write 2 ren data in output register t frl (1) low t skew1 t skew1 t frl (1) t ref data read 2680 drw 09 t enh
9 commercial temperature range idt72420/72200/72210/72220/72230/72240 cmos syncfifo? 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 notes: 1. t skew2 is the minimum time between a rising rclk edge and a rising wclk edge for af to change during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew2 , then af may not change state until the next wclk edge. 2. if a write is performed on this rising edge of the write clock, there will be full -7 words in the fifo when af goes low. figure 8. almost full flag timing notes: 1. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge for ae to change during the current clock cycle. if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then ae may not change state until the next rclk edge. 2. if a read is performed on this rising edge of the read clock, there will be empty +7 words in the fifo when ae goes low. figure 9. almost empty flag timing wclk wen t ens ae t enh t clkh t clkl t ae rclk ren t ens empty+7 empty+8 t skew2 (1) t enh (2) t ae 2680 drw 11 wclk wen t ens af t enh t clkh t clkl rclk ren t ens t skew2 (1) full - 8 words in fifo full - 7 words in fifo (2) t af t af t enh 2680 drw10
10 commercial temperature range idt72420/72200/72210/72220/72230/72240 cmos syncfifo? 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 figure 10. block diagram of single 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 synchronous fifo width expansion configuration - word width may be increased simply by connecting the corresponding input control signals of multiple devices. a composite flag should be created for each of the endpoint status flags ( ef and ff ) the partial status flags ( ae and af ) can be detected from any one device. figure 11 demonstrates a 16-bit word width by using two idt72420/72200/72210/72220/72230/72240s. any word width can be attained by adding additional idt72420/72200/72210/72220/72230/72240s. figure 11. block diagram of 64 x 16, 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, 4,096 x 16 synchronous fifo used in a width expansion configuration write clock (wclk) read clock (rclk) read enable ( ren ) output enable ( oe ) full flag ( ff ) almost-full ( af ) empty flag ( ef ) almost-empty( ae ) idt 72420 72200 72210 72220 72230 72240 reset ( rs ) write enable ( wen ) data in (d 0- d 7 ) data out (q 0 -q 7 ) 2680 drw 12 data in (d) write clock (wclk) 16 8 8 reset ( rs ) read clock (rclk) data out (q) 8 16 write enable ( wen ) full flag ( ff ) #1 almost-empty ( ae ) empty flag ( ef ) #2 output enable ( oe ) read enable ( ren ) 8 idt 72420 72200 72210 72220 72230 72240 full flag ( ff ) #2 empty flag ( ef ) #1 reset ( rs ) idt 72420 72200 72210 72220 72230 72240 2680 drw13 almost-full ( af ) operating configurations single device configuration - a single idt72420/72200/72210/ 72220/72230/72240 may be used when the application requirements are for 64/256/512/1,024/2,048/4,096 words or less. see figure 10.
11 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-360-1753 san jose, ca 95138 fax: 408-284-2775 email: fifohelp@idt.com www.idt.com depth expansion the idt72420/72200/72210/72220/72230/72240 can be adapted to applications when the requirements are for greater than 64/256/512/1,024/ 2,048/4,096 words. depth expansion is possible by using expansion logic to direct the flow of data. a typical application would have the expansion logic alternate data accesses from one device to the next in a sequential manner. please see the application note ?depth expansion idt's synchronous fifos using ring counter approach? for details of this configuration. ordering information notes: 1. industrial temperature range is available by special order. 2. green parts are available. for specific speeds and packages contact your sales office. xxxxx devicetype x power xx speed xx package x process / temperature range low power l 10 15 25 commercial blank commercial (0 c to +70 c) tp plastic thin dip (300 mil, p28-2) clock cycle time (t clk ) speed in nanoseconds 72420 72200 72210 72220 72230 72240 64x 8 syncfifo 256 x 8 syncfifo 512 x 8 syncfifo 1,024 x 8 syncfifo 2,048 x 8 syncfifo 4,098 x 8 syncfifo 2680 drw14 x g green datasheet document history 10/03/2000 pgs. 1, 3, 4 and 11. 05/01/2001 pgs. 1, 2, 3, 4 and 11. 02/10/2006 pgs. 1 and 11. 01/08/2009 pg. 11. 07/25/2013 pgs. 1, 3, 9 and 10.

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